Field of the Invention
The present invention relates to a semiconductor integrated device and, more particualarly, to a semiconductor device comprising a bipolar transistor and a complementary MOS transistor formed on a single semiconductor substrate, and to a manufacturing method thereof.
A semiconductor integrated device wherein both a bipolar transistor and a complementary MOS transistor are formed on a single semiconductor substrate is generally called a Bi-CMOS. The Bi-CMOS is a relatively new semiconductor integrated device (IC) and was developed so as to meet the demand for an IC including both analog and digital functions in a single semiconductor chip. An IC having both analog and digital functions can consist of an Integrated Injection Logic (I.sup.2 L) or a CMOS. However, in a Bi-CMOS, analog processing is performed by a bipolar element which is suitable therefor, and digital processing is performed by a CMOS element which is suitable therefor, so that the Bi-CMOS can have features of both the bipolar and CMOS elements. Therefore, the Bi-CMOS is expected to extend the application fields of an analog/digital IC.
Needless to say, the Bi-CMOS has its own problem, i.e., a latch up phenomenon which is characteristic to the CMOS structure. However, in order to prevent this latch up phenomenon of the Bi-CMOS, not only the CMOS part but also the whole structure of the Bi-CMOS must be considered. In this respect, the Bi-CMOS shown in FIG. 1, which is available for preventing the latch up phenomenon and in which both a bipolar transistor having a large current drive capacity and a CMOS are formed on a single substrate, is suggested (IBM Technical Disclosure Bulletin; Vol. 16, No. 18, 1974, pp. 2,719 and 2,720).
In FIG. 1, reference numeral 1 denotes a p-type silicon substrate. A p-type epitaxial silicon layer 2 is formed on the p-type silicon substrate 1. Two high concentration n.sup.+ -type buried layers 3a and 3b are partially buried in both the substrate 1 and the epitaxial layer 2. N-type well regions 4a and 4b (referred as n-wells hereafter) are formed extending downward from the surface of the epitaxial layer 2 to the surfaces of the n.sup.+ -type buried layers 3a and 3b, respectively. The n-well 4b serves as an element region of a bipolar transistor; a vertical npn transistor 30 is formed as shown in FIG. 1. The npn transistor 30 is electrically isolated from the other elements by a p-n junction with a p-type region surrounding it. The other n-well 4a and the p-type epitaxial layer 2 adjacent thereto serve as an element region of a CMOS. Then, an n-channel MOS transistor (n-MOSFET) 20 and a p-channel MOS transistor (p-MOSFET) 10 are respectively formed in the n-well 4a and the p-type epitaxial layer 2. Reference numeral 5 denotes a silicon oxide film.
In the Bi-CMOS structure of FIG. 1, the n.sup.+ -type buried layer 3a is formed under the n-well 4a . Therefore, of parasitic transistors causing the latch up phenomenon in the CMOS part, a vertical parasitic pnp transistor formed in the n-MOSFET 20 has a small h.sub.FE and is, therefore, available for preventing the latch up phenomenon. However, the operations of a lateral parasitic pnp and npn transistors in the CMOS part cannot be prevented. Furthermore, the presence of the n.sup.+ -type buried layers 3a and 3b results in an easy operation of the lateral parasitic npn transistor consisting of the n-wells 4a and 4b and the p-type region therebetween, and this parasitic transistor is inherent to the Bi-CMOS.
As described above, the structure of FIG. 1 cannot completely prevent the latch up phenomenon.
In this manner, a Bi-CMOS, which is regarded as being able to prevent the latch up phenomenon and in which both a CMOS and a bipolar transistor are formed, is known; though it is not sufficient as described above. However, a Bi-CMOS (referred as CBi-CMOS hereafter) in which complementary bipolar transistors are used as a bipolar transistor is not yet known. The Bi-CMOS without complementary bipolar transistors generally has the following defects.
When a power supply voltage is low, an open gain of an operational amplifier (Op-Amp) is also low and it is difficult to obtain a wide frequency range. In addition, when a power supply voltage is low, it is also difficult to provide a wide dynamic range. Furthermore, it is difficult to constitute an output stage having a large current flow, a large output and, in this case, a high speed.
In this manner, a strong demand has arisen for a CBi-CMOS in which both a complementary bipolar transistor and a CMOS are formed.